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| LTC1854/LTC1855/LTC1856 8-Channel, 10V Input 12-/14-/16-Bit, 100ksps ADC Converters with Shutdown DESCRIPTIO The LTC(R)1854/LTC1855/LTC1856 are 8-channel, low power, 12-/14-/16-bit, 100ksps, analog-to-digital converters (ADCs). These ADCs operate from a single 5V supply and the 8-channel multiplexer can be programmed for single-ended inputs, pairs of differential inputs, or combinations of both. In addition, all channels are fault protected to 30V. A fault condition on any channel will not affect the conversion result of the selected channel. An onboard precision reference minimizes external components. Power dissipation is 40mW at 100ksps and lower in two power shutdown modes (27.5mW in Nap mode and 40mW in Sleep mode.) DC specifications include 3LSB INL for the LTC1856, 1.5LSB INL for the LTC1855 and 1LSB for the LTC1854. The internal clock is trimmed for 5ms maximum conversion time and the sampling rate is guaranteed at 100ksps. A separate convert start input and data ready signal (BUSY) ease connections to FIFOs, DSPs and microprocessors. , LT, LTC and LTM are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners. FEATURES Single 5V Supply Sample Rate: 100ksps 8-Channel Multiplexer with 30V Protection 10V Bipolar Input Range Single Ended or Differential 3LSB INL for the LTC1856, 1.5LSB INL for the LTC1855, 1LSB INL for the LTC1854 Power Dissipation: 40mW (Typ) SPI/MICROWIRETM Compatible Serial I/O Power Shutdown: Nap and Sleep SINAD: 87dB (LTC1856) Operates with Internal or External Reference Internal Synchronized Clock 28-Pin SSOP Package APPLICATIO S Industrial Process Control Multiplexed Data Acquisition Systems High Speed Data Acquisition for PCs Digital Signal Processing TYPICAL APPLICATIO 100kHz, 12-Bit/14-/16-Bit Sampling ADC 2.0 SOFTWARE-PROGRAMMABLE SINGLE-ENDED OR DIFFERENTIAL INPUTS 10V BIPOLAR INPUT RANGE COM CONVST CH0 LTC1854/ RD CH1 LTC1855/ SCK CH2 LTC1856 SDI CH3 DGND CH4 SDO CH5 BUSY CH6 OVDD DVDD CH7 + AVDD MUXOUT MUXOUT - AGND3 ADC+ AGND2 ADC- REFCOMP AGND1 VREF INL (LSB) P CONTROL LINES 3V TO 5V 5V 5V 0.1F 10F 10F 0.1F 10F 0.1F 2.5V 1F 10F 0.1F U U U LTC1856 Typical INL Curve 1.5 1.0 0.5 0 -0.5 -1.0 -1.5 -2.0 -32768 -16384 0 CODE 185456 G01 16384 32767 185456fa 1 LTC1854/LTC1855/LTC1856 ABSOLUTE (Notes 1, 2) AXI U RATI GS PACKAGE/ORDER I FOR ATIO TOP VIEW COM CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7 1 2 3 4 5 6 7 8 9 28 CONVST 27 RD 26 SCK 25 SDI 24 DGND 23 SDO 22 BUSY 21 OVDD 20 DVDD 19 AVDD 18 AGND3 17 AGND2 16 REFCOMP 15 VREF Supply Voltage (OVDD = DVDD = AVDD = VDD) ........... 6V Ground Voltage Difference DGND, AGND1, AGND2, AGND3 ...................... 0.3V Analog Input Voltage ADC+, ADC- (Note 3) ...................(AGND1 - 0.3V) to (AVDD + 0.3V) CH0-CH7, COM .................................................. 30V Digital Input Voltage (Note 4) ...... (DGND - 0.3V) to 10V Digital Output Voltage .... (DGND - 0.3V) to (DVDD + 0.3V) Power Dissipation .............................................. 500mW Operating Temperature Range LTC1854C/LTC1855C/LTC1856C ............ 0C to 70C LTC1854I/LTC1855I/LTC1856I .......... - 40C to 85C Storage Temperature Range ................. - 65C to 150C Lead Temperature (Soldering, 10 sec) ................. 300C MUXOUT + 10 MUXOUT - 11 ADC + 12 ADC - 13 AGND1 14 G PACKAGE 28-LEAD PLASTIC SSOP TJMAX = 110C, qJA = 95C/W ORDER PART NUMBER LTC1854CG LTC1854IG LTC1855CG LTC1855IG LTC1856CG LTC1856IG Order Options Tape and Reel: Add #TR Lead Free: Add #PBF Lead Free Tape and Reel: Add #TRPBF Lead Free Part Marking: http://www.linear.com/leadfree/ Consult LTC Marketing for parts specified with wider operating temperature ranges. CO VERTER A D PARAMETER Resolution No Missing Codes Transition Noise Integral Linearity Error Differential Linearity Error Bipolar Zero Error Bipolar Zero Error Drift Bipolar Zero Error Match Bipolar Full-Scale Error Bipolar Full-Scale Error Drift The denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. MUXOUT connected to ADC inputs. (Notes 5, 6) CONDITIONS ULTIPLEXER CHARACTERISTICS MIN 12 12 LTC1854 TYP MAX MIN 14 14 LTC1855 TYP MAX MIN 16 15 LTC1856 TYP MAX 0.06 (Note 7) (Note 8) 0.25 1 1 5 3 0.34 0.45 -1 0.1 1.5 1.5 8 4 0.14 0.40 -2 1 -1 0.1 0.1 External Reference (Note 11) Internal Reference (Note 11) External Reference Internal Reference 2.5 7 10 96 2.5 7 10 96 2.5 7 10 96 Bipolar Full-Scale Error Match Input Common Mode Range Input Common Mode Rejection Ratio 5 10 UNITS Bits Bits LSBRMS 3 LSB 4 LSB 23 LSB ppm/C 10 LSB 0.1 % 0.4 % ppm/C ppm/C 15 LSB V dB 185456fa 2 U W U U WW WU W U LTC1854/LTC1855/LTC1856 A ALOG I PUT The denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. (Note 5) PARAMETER Analog Input Range Impedance Capacitance CONDITIONS CH0 to CH7, COM ADC+, ADC- (Note 3) CH0 to CH7, COM MUXOUT+ , MUXOUT- CH0 to CH7, COM Sample Mode ADC+, ADC- Hold Mode ADC+, ADC- Input Leakage Current ADC+, ADC-, CONVST = Low DY A IC ACCURACY SYMBOL THD PARAMETER Total Harmonic Distortion The denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. MUXOUT connected to ADC inputs. (Note 5) CONDITIONS 1kHz Input Signal, First Five Harmonics 1kHz Input Signal 1kHz Input Signal MIN LTC1854 TYP MAX 74 -102 -99 -120 1 -70 60 Full-Scale Step (Note 9) (Note 12) 150 4 150 MIN LTC1855 TYP MAX 83 -95 -99 -120 1 -70 60 4 150 MIN LTC1856 TYP MAX 87 -101 -103 -120 1 -70 60 4 UNITS dB dB dB dB MHz ns ps ms ns S/(N + D) Signal-to-(Noise + Distortion) Ratio 1kHz Input Signal Peak Harmonic or Spurious Noise Channel-to-Channel Isolation -3dB Input Bandwidth Aperture Delay Aperture Jitter Transient Response Overvoltage Recovery U WU U MIN TYP 10 ADC - 2.048 31 5 5 12 4 MAX UNITS V V kW kW pF pF pF 1 mA 185456fa 3 LTC1854/LTC1855/LTC1856 The denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. (Note 5) PARAMETER VREF Output Voltage VREF Output Temperature Coefficient VREF Output Impedance VREFCOMP Output Voltage CONDITIONS IOUT = 0 IOUT = 0 -0.1mA IOUT 0.1mA IOUT = 0 I TER AL REFERE CE CHARACTERISTICS DIGITAL I PUTS A D DIGITAL OUTPUTS SYMBOL VIH VIL IIN CIN VOH VOL IOZ COZ ISOURCE ISINK PARAMETER High Level Input Voltage Low Level Input Voltage Digital Input Current Digital Input Capacitance High Level Output Voltage Low Level Output Voltage Hi-Z Output Leakage Hi-Z Output Capacitance Output Source Current Output Sink Current CONDITIONS VDD = 5.25V VDD = 4.75V VIN = 0V to VDD The denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. (Note 5) MIN POWER REQUIRE E TS PARAMETER Positive Supply Voltage Positive Supply Current Nap Mode Sleep Mode Power Dissipation Nap Mode Sleep Mode The denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. (Note 5) CONDITIONS (Notes 9 and 10) 4 UW U U U U U MIN 2.475 TYP 2.50 10 8 4.096 MAX 2.525 UNITS V ppm/C kW V TYP MAX 0.8 10 UNITS V V mA pF V V 2.4 5 VDD = 4.75V, IO = -10mA, OVDD = VDD VDD = 4.75V, IO = -200mA, OVDD = VDD VDD = 4.75V, IO = 160mA, OVDD = VDD VDD = 4.75V, IO = 1.6mA, OVDD = VDD VOUT = 0V to VDD, RD = High RD = High VOUT = 0V VOUT = VDD 4.74 4 0.05 0.10 15 -10 10 0.4 10 V V mA pF mA mA MIN 4.75 TYP 5.00 8.0 5.5 8.0 40.0 27.5 40.0 MAX 5.25 12 7 13 UNITS V mA mA mA mW mW mW CONVST = 0V or 5V CONVST = 0V or 5V 185456fa LTC1854/LTC1855/LTC1856 TI I G CHARACTERISTICS SYMBOL PARAMETER fSAMPLE(MAX) Maximum Sampling Frequency tCONV tACQ fSCK tr tf t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 Conversion Time Acquisition Time SCK Frequency SDO Rise Time SDO Fall Time CONVST High Time CONVST to BUSY Delay SCK Period SCK High SCK Low Delay Time, SCKO to SDO Valid Time from Previous SDO Data Remains Valid After SCKO SDO Valid After RDO RDO to SCK Setup Time SDI Setup Time Before SCK SDI Hold Time After SCK SDO Valid Before BUSY Bus Relinquish Time RD = Low, CL = 25pF, See Test Circuits See Test Circuits CL = 25pF, See Test Circuits CL = 25pF, See Test Circuits CL = 25pF, See Test Circuits CL = 25pF, See Test Circuits Through CH0 to CH7 Inputs Through ADC+ , ADC- Only (Note 13) See Test Circuits See Test Circuits The denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. (Note 5) CONDITIONS Through CH0 to CH7 Inputs Through ADC+ , ADC- Only Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: All voltage values are with respect to ground with DGND, AGND1, AGND2 and AGND3 wired together unless otherwise noted. Note 3: When these pin voltages are taken below ground or above AVDD = DVDD = OVDD = VDD, they will be clamped by internal diodes. This product can handle currents of greater than 100mA below ground or above VDD without latchup. Note 4: When these pin voltages are taken below ground they will be clamped by internal diodes. This product can handle currents of greater than 100mA below ground without latchup. These pins are not clamped to VDD. Note 5: VDD = 5V, fSAMPLE = 100kHz, tr = tf = 5ns unless otherwise specified. Note 6: Linearity, offset and full-scale specifications apply for a singleended analog MUX input with respect to ground or ADC+ with respect to ADC- tied to ground. UW MIN 100 TYP 166 4 1 MAX UNITS kHz kHz 5 4 ms ms ms MHz ns ns ns 0 6 6 40 15 50 10 10 25 5 20 11 20 0 7 5 20 10 20 30 ns ns ns ns 45 ns ns 30 ns ns ns ns ns 30 ns Note 7: Integral nonlinearity is defined as the deviation of a code from a straight line passing through the actual end points of the transfer curve. The deviation is measured from the center of the quantization band. Note 8: Bipolar zero error is the offset voltage measured from - 0.5LSB when the output code flickers between 0000 0000 0000 0000 and 1111 1111 1111 1111 for the LTC1856, between 00 0000 0000 0000 and 11 1111 1111 1111 for the LTC1855 and between 0000 0000 0000 and 1111 1111 1111 for the LTC1854. Note 9: Guaranteed by design, not subject to test. Note 10: Recommended operating conditions. Note 11: Full-scale bipolar error is the worst case of -FS or +FS untrimmed deviation from ideal first and last code transitions, divided by the full-scale range, and includes the effect of offset error. Note 12: Recovers to specified performance after (2 * FS) input overvoltage. Note 13: t6 of 45ns maximum allows fSCK up to 10MHz for rising capture with 50% duty cycle and fSCK up to 20MHz for falling capture (with 5ns setup time for the receiving logic). 185456fa 5 LTC1854/LTC1855/LTC1856 TYPICAL PERFOR A CE CHARACTERISTICS LTC1856 Typical INL Curve 2.0 1.5 1.0 2.0 1.5 1.0 0 -0.5 -1.0 -1.5 -2.0 -32768 -16384 0 CODE 185456 G01 DNL (LSB) INL (LSB) 0.5 0.5 0 -0.5 -1.0 -1.5 16384 32767 -2.0 -32768 -16384 0 CODE 16384 32767 185456 G02 MAGNITUDE (dB) LTC1855 Typical INL Curve 1 0.8 0.6 0.4 DNL (LSB) INL (LSB) 1 0.8 0.6 0.2 0 -0.2 -0.4 -0.6 -0.8 -1 -8192 -4096 0 CODE 185455 G04 0.2 0 -0.2 -0.4 -0.6 -0.8 4096 8191 -1 -8192 MAGNITUDE (dB) LTC1854 Typical INL Curve 1.0 0.8 0.6 0.4 1.0 0.8 0.6 DNL (LSB) INL (LSB) 0.2 0 -0.2 -0.4 -0.6 -0.8 -1.0 -2048 -1024 0 CODE 1024 2047 185456 G07 0.2 0 -0.2 -0.4 -0.6 -0.8 -1.0 -2048 -1024 0 CODE 1024 2047 185456 G08 MAGNITUDE (dB) 6 UW LTC1856 Typical DNL Curve 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 LTC1856 Nonaveraged 4096-Point FFT Plot fSAMPLE = 100kHz fIN = 1kHz SINAD = 87dB THD = -101dB 0 5 10 15 20 25 30 35 40 45 50 FREQUENCY (kHz) 185456 G03 LTC1855 Typical DNL Curve 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 LTC1855 Nonaveraged 4096-Point FFT Plot fSAMPLE = 100kHz fIN = 1kHz SINAD = 83dB THD = -95dB 0.4 -4096 0 CODE 4096 8191 185456 G05 0 5 10 15 20 25 30 35 40 45 50 FREQUENCY (kHz) 185456 G06 LTC1854 Typical DNL Curve 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 LTC1854 Nonaveraged 4096-Point FFT Plot fSAMPLE = 100kHz fIN = 1kHz SINAD = 73.6dB THD = -102dB 0.4 0 10 30 20 FREQUENCY (kHz) 40 50 185456 G09 185456fa LTC1854/LTC1855/LTC1856 TYPICAL PERFOR A CE CHARACTERISTICS LTC1856 SINAD vs Input Frequency 90 TOTAL HARMONIC DISTORTION (dB) 88 86 SINAD (dB) 84 82 80 78 76 74 1 10 INPUT FREQUENCY (kHz) 100 185456 G10 CHANNEL-TO-CHANNEL OFFSET ERROR MATCHING (LSBs) LTC1855 SINAD vs Input Frequency 85 TOTAL HARMONIC DISTORTION (dB) 80 -70 CHANNEL-TO-CHANNEL OFFSET ERROR MATCHING (LSBs) SINAD (dB) 75 70 65 60 1 10 INPUT FREQUENCY (kHz) 100 185456 G13 LTC1854 SINAD vs Input Frequency 80 TOTAL HARMONIC DISTORTION (dB) -60 -70 CHANNEL-TO-CHANNEL OFFSET ERROR MATCHING (LSB) 75 SINAD (dB) 70 65 60 1 10 INPUT FREQUENCY (kHz) 100 185456 G16 UW LTC1856 Total Harmonic Distortion vs Input Frequency -70 1.0 LTC1856 Channel-to-Channel Offset Error Matching vs Temperature -80 0.5 -90 0 -100 -0.5 -110 1 10 INPUT FREQUENCY (kHz) 100 185456 G11 -1.0 -50 -25 0 25 50 TEMPERATURE (C) 75 100 185456 G12 LTC1855 Total Harmonic Distortion vs Input Frequency -60 0.5 LTC1855 Channel-to-Channel Offset Error Matching vs Temperature 0.25 -80 0 -90 -0.25 -100 -110 1 10 INPUT FREQUENCY (kHz) 100 185456 G14 -0.5 -50 -25 0 25 50 TEMPERATURE (C) 75 100 185456 G15 LTC1854 Total Harmonic Distortion vs Input Frequency 0.25 0.20 0.15 0.10 0.05 0 -0.05 -0.10 -0.15 -0.20 -110 1 10 INPUT FREQUENCY (kHz) 100 185456 G17 LTC1854 Channel-to-Channel Offset Error Matching vs Temperature -80 -90 -100 -0.25 -50 -25 25 50 0 TEMPERATURE (C) 75 100 185456 G18 185456fa 7 LTC1854/LTC1855/LTC1856 TYPICAL PERFOR A CE CHARACTERISTICS LTC1856 Channel-to-Channel Gain Error Matching vs Temperature 1.0 0.5 CHANNEL-TO-CHANNEL GAIN ERROR MATCHING (LSBs) CHANNEL-TO-CHANNEL GAIN ERROR MATCHING (LSBs) 0.5 0.25 CHANNEL-TO-CHANNEL GAIN ERROR MATCHING (LSB) 0 -0.5 -1.0 -50 -25 0 25 50 TEMPERATURE (C) Internal Reference Voltage vs Temperature 2.520 INTERNAL REFERENCE VOLTAGE (V) CHANGE IN REFCOMP VOLTAGE (V) 2.515 2.510 2.505 2.500 2.495 2.490 2.485 2.480 -50 -25 50 25 TEMPERATURE (C) 0 75 100 POWER SUPPLY FEEDTHROUGH (dB) Supply Current vs Supply Voltage 9.0 fSAMPLE = 100kHz POSITIVE SUPPLY CURRENT (mA) SUPPLY CURRENT (mA) 8.5 8.0 7.5 7.0 4.5 5 5.25 4.75 SUPPLY VOLTAGE (V) 8 UW 75 LTC1855 Channel-to-Channel Gain Error Matching vs Temperature LTC1854 Channel-to-Channel Gain Error Matching vs Temperature 0.25 0.20 0.15 0.10 0.05 0 -0.05 -0.10 -0.15 -0.20 0 -0.25 100 -0.5 -50 -25 0 25 50 TEMPERATURE (C) 75 100 -0.25 -50 -25 25 50 0 TEMPERATURE (C) 75 100 185456 G19 185456 G20 185456 G21 Change in REFCOMP Voltage vs Load Current 0.04 LTC1856 Power Supply Feedthrough vs Ripple Frequency -10 -20 -30 -40 -50 -60 -70 -80 100 fSAMPLE = 100kHz VRIPPLE = 60mV 0.02 0 -0.02 -0.04 -50 -40 -30 -20 -10 LOAD CURRENT (mA) 0 10 185456 G23 1k 10k 100k RIPPLE FREQUENCY (Hz) 1M 185456 G24 185456 G22 Supply Current vs Temperature 9.0 fSAMPLE = 100kHz 8.5 8.0 7.5 5.5 185454 G25 7.0 -50 -25 0 25 50 TEMPERATURE (C) 75 100 185456 G26 185456fa LTC1854/LTC1855/LTC1856 PI FU CTIO S COM (Pin 1): Common Input. This is the negative reference point for all single-ended inputs. It must be free of noise and is usually connected to the analog ground plane. CH0 (Pin 2): Analog MUX Input. CH1 (Pin 3): Analog MUX Input. CH2 (Pin 4): Analog MUX Input. CH3 (Pin 5): Analog MUX Input. CH4 (Pin 6): Analog MUX Input. CH5 (Pin 7): Analog MUX Input. CH6 (Pin 8): Analog MUX Input. CH7 (Pin 9): Analog MUX Input. (Pin 10): Positive MUX Output. Output of the analog multiplexer. Connect to ADC + for normal operation. MUXOUT - (Pin 11): Negative MUX Output. Output of the analog multiplexer. Connect to ADC - for normal operation. ADC + (Pin 12): Positive Analog Input to the Analog-toDigital Converter. ADC - (Pin 13): Negative Analog Input to the Analog-toDigital Converter. MUXOUT + AGND1 (Pin 14): Analog Ground. VREF (Pin 15): 2.5V Reference Output. Bypass to analog ground with a 1mF tantalum capacitor. REFCOMP (Pin 16): Reference Buffer Output. Bypass to analog ground with a 10mF tantalum and a 0.1mF ceramic capacitor. Nominal output voltage is 4.096V. AGND2 (Pin 17): Analog Ground. AGND3 (Pin 18): Analog Ground. This is the substrate connection. AVDD (Pin 19): 5V Analog Supply. Bypass to analog ground with a 0.1mF ceramic and a 10mF tantalum capacitor. DVDD (Pin 20): 5V Digital Supply. Bypass to digital ground with a 0.1mF ceramic and a 10mF tantalum capacitor. OVDD (Pin 21): Positive Supply for the Digital Output Buffers (3V to 5V). Bypass to digital ground with a 0.1mF ceramic and a 10mF tantalum capacitor. BUSY (Pin 22): Output shows converter status. It is low when a conversion is in progress. SDO (Pin 23): Serial Data Output. U U U 185456fa 9 LTC1854/LTC1855/LTC1856 PI FU CTIO S DGND (Pin 24): Digital Ground. SDI (Pin 25): Serial Data Input. SCK (Pin 26): Serial Data Clock. RD (Pin 27): Read Input. This active low signal enables the digital output pin SDO and enables the serial interface, SDI and SCK are ignored when RD is high. CONVST (Pin 28): Conversion Start. The ADC starts a conversion on CONVST's rising edge. FU CTIO AL BLOCK DIAGRA CH0 CH1 2 3 * * * 9 1 INPUT MUX CH7 COM MUXOUT- 14 AGND1 MUXOUT+ 11 10 ADC+ 10 W U U U U U AVDD 19 DVDD 20 MUX ADDRESS CONTROL LOGIC INTERNAL CLOCK 28 25 22 CONVST SDI BUSY 26 SCK + 12-/14-/16-BIT SAMPLING ADC DATA OUT SERIAL I/O 27 21 23 RD OVDD SDO - 4.096V 2.5V REFERENCE 1.6384X 8k ADC- 12 13 15 VREF 16 REFCOMP 17 18 24 AGND2 AGND3 DGND 18545 BD 185456fa LTC1854/LTC1855/LTC1856 TEST CIRCUITS Load Circuits for Access Timing 5V 1k DN 1k 25pF DN 25pF DN 1k 25pF DN 25pF Load Circuits for Output Float Delay 5V 1k (A) Hi-Z TO VOH AND VOL TO VOH (B) Hi-Z TO VOL AND VOH TO VOL 18545 TC01 (A) VOH TO Hi-Z (B) VOL TO Hi-Z 18545 TC02 TI I G DIAGRA S t 2 (CONVST to BUSY Delay) t2 t1 (For Short Pulse Mode) t1 CONVST 50% 50% 18545 TD01 t3, t4, t5 (SCK Timing) SCK t4 SCK t3 t8 (SDO Valid After RD ) t8 RD RD 0.4V SDO Hi-Z W UW CONVST 2.4V BUSY 0.4V 18545 TD02 t 6 (Delay Time, SCK to SDO Valid) t7 (Time from Previous Data Remains Valid After SCK ) t6 t7 0.4V t5 SDO 18545 TD03 2.4V 0.4V 18545 TD04 t9 (RD to SCK Setup Time) t9 0.4V 2.4V 0.4V 18545 TD05 SCK 2.4V 18545 TD06 185456fa 11 LTC1854/LTC1855/LTC1856 TI I G DIAGRA S t 10 (SDI Setup Time Before SCK ) t10 SCK 2.4V SDI 2.4V 0.4V 18545 TD07 t 12 (SDO Valid Before BUSY , RD = 0) t12 BUSY 2.4V RD SDO 2.4V 12 W UW t11 (SDI Hold Time After SCK ) t11 SCK 2.4V SDI 2.4V 0.4V 18545 TD08 t 13 (BUS Relinquish Time) t13 2.4V B15 18545 TD09 SDO 90% 10% Hi-Z 18545 TD10 185456fa LTC1854/LTC1855/LTC1856 APPLICATIO S I FOR ATIO OVERVIEW The LTC1854/LTC1855/LTC1856 are innovative, multichannel ADCs. The on-chip resistors provide attenuation and offset for each channel. The precisely trimmed attenuators ensure an accurate input range. Because they precede the multiplexer, errors due to multiplexer on-resistance are eliminated. The input word selects the single ended or differential inputs for each channel or pair of channels. Overrange protection is provided for unselected channels. An overrange condition on an unused channel will not affect the conversion result on the selected channel. CONVERSION DETAILS The LTC1854/LTC1855/LTC1856 use a successive approximation algorithm and an internal sample-and-hold circuit to convert an analog signal to a 12-/14-/16-bit serial output respectively. The ADCs are complete with a precision reference and an internal clock. The control logic provides easy interface to microprocessors and DSPs. (Please refer to the Digital Interface section for the data format.) The analog signals applied at the MUX input channels are rescaled by the resistor divider network formed by R1, R2 and R3 as shown below. The rescaled signals appear on the MUXOUT (Pins 10, 11) which are also connected to the ADC inputs (Pins 12, 13) under normal operation. REFCOMP MUX INPUT R1 25k R3 10k R2 17k CH SEL MUXOUT 18545 AI01 U Before starting a conversion, an 8-bit data word is clocked into the SDI input on the first eight rising SCK edges to select the MUX address and power down mode. The ADC enters acquisition mode on the falling edge of the sixth clock in the 8-bit data word and ends on the rising edge of the CONVST signal which also starts a conversion (see Figure 7). A minimum time of 4ms will provide enough time for the sample-and-hold capacitors to acquire the analog signal. Once a conversion cycle has begun, it cannot be restarted. During the conversion, the internal differential 12-/14-/16bit capacitive DAC output is sequenced by the SAR from the most significant bit (MSB) to the least significant bit (LSB). The input is successively compared with the binary weighted charges supplied by the differential capacitive DAC. Bit decisions are made by a high speed comparator. At the end of a conversion, the DAC output balances the analog input (ADC + - ADC -). The SAR contents (a 12-/14/16-bit data word) which represents the difference of ADC+ and ADC- are loaded into the 12-/14-/16-bit shift register. DRIVING THE ANALOG INPUTS The input range for the LTC1854/LTC1855/LTC1856 is 10V and the MUX inputs are overvoltage protected to 30V. The input impedance is typically 31kW; therefore, it should be driven with a low impedance source. Wideband noise coupling into the input can be minimized by placing a 3000pF capacitor at the input as shown in Figure 2. An NPO-type capacitor gives the lowest distortion. Place the capacitor as close to the device input pin as possible. If an amplifier is to be used to drive the input, care should be taken to select an amplifier with adequate accuracy, linearity and noise for the application. The following list is a summary of the op amps that are suitable for driving the LTC1854/LTC1855/LTC1856. More detailed information is available in the Linear Technology data books and online at www.linear.com. LT(R)1007: Low noise precision amplifier. 2.7mA supply current 5V to 15V supplies. Gain bandwidth product 8MHz. DC applications. 185456fa W UU 13 LTC1854/LTC1855/LTC1856 APPLICATIO S I FOR ATIO U AVDD DVDD MUX ADDRESS CONTROL LOGIC INTERNAL CLOCK CONVST SDI BUSY SCK CH0 CH1 * * * INPUT MUX CH7 COM MUXOUT- AGND1 Figure 1. LTC1854/LTC1855/LTC1856 Simplified Equivalent Circuit AIN+ 3000pF AIN- CH1 * * * * MUXOUT+ MUXOUT- ADC+ ADC- 18545 F02 CH0 Figure 2. Analog Input Filtering LT1227: 140MHz video current feedback amplifier. 10mA supply current. 5V to 15V supplies. Low noise and low distortion. LT1468/LT1469: Single and dual 90MHz, 16-bit accurate op amp. Good AC/DC specs. 5V to 15V supplies. LT1677: Single, low noise op amp. Rail-to-rail input and output. Up to 15V supplies. 14 W UU + 12-/14-/16-BIT SAMPLING ADC DATA OUT SERIAL I/O RD OVDD SDO 4.096V 2.5V REFERENCE 1.6384X - 8k MUXOUT+ ADC+ ADC- VREF REFCOMP 18545 F01 AGND2 AGND3 DGND LT1792: Single, low noise JFET input op amp, 5V supplies. LT1793: Single, low noise JFET input op amp, 10pA bias current, 5V supplies. LT1881/LT1882: Dual and quad, 200pA bias current, railto-rail output op amps. Up to 15V supplies. LT1844/LT1885: Dual and quad, 400pA bias current, railto-rail output op amps. Up to 15V supplies. Faster response and settling time. INTERNAL VOLTAGE REFERENCE The LTC1854/LTC1855/LTC1856 have an on-chip, temperature compensated, curvature corrected, bandgap reference, which is factory trimmed to 2.50V. The full-scale range of the LTC1854/LTC1855/LTC1856 is equal to 10V. The output of the reference is connected to the input of a gain of 1.6384x buffer through an 8k resistor (see Figure 3). The input to the buffer or the output of the reference is 185456fa LTC1854/LTC1855/LTC1856 APPLICATIO S I FOR ATIO available at VREF (Pin 15). The internal reference can be overdriven with an external reference if more accuracy is needed. The buffer output drives the internal DAC and is available at REFCOMP (Pin 16). The REFCOMP pin can be used to drive a steady DC load of less than 2mA. Driving an AC load is not recommended because it can cause the performance of the converter to degrade. 2.5V 15 VREF 1F 8k 2.5V REFERENCE 12-/14-/16-BIT CAPACITIVE DAC 4.096V 0.1F 1.6384X BUFFER 16 REFCOMP 18545 F03 10F Figure 3. Internal or External Reference Source For minimum code transition noise the VREF pin and the REFCOMP pin should each be decoupled with a capacitor to filter wideband noise from the reference and the buffer. FULL SCALE AND OFFSET Figure 4 shows the ideal input/output characteristics for the LTC1856. The code transitions occur midway between 011...111 011...110 OUTPUT CODE 000...001 000...000 111...111 111...110 100...001 100...000 - (FS - 1LSB) INPUT VOLTAGE (V) 18545 F04 FS - 1LSB Figure 4. Bipolar Transfer Characteristics U successive integer LSB values (i.e., -FS+0.5LSB, -FS+1.5LSB, -FS+2.5LSB, ... FS-1.5LSB, FS-0.5LSB). The output is two's complement binary with: 1 LSB = FS - (-FS) 20V = = 305.2mV 65566 65536 W UU In applications where absolute accuracy is important, offset and full-scale errors can be adjusted to zero during a calibration sequence. Offset error must be adjusted before full-scale error. Zero offset is achieved by adjusting the offset applied to the "-" input. For single-ended inputs, this offset should be applied to the COM pin. For differential inputs, the "-" input is dictated by the MUX address. For zero offset error, apply - 0.5LSB to the "+" input and adjust the offset at the "-" input until the output code flickers between 0000 0000 0000 0000 and 1111 1111 1111 1111 for the LTC1856, between 00 0000 0000 0000 and 11 1111 1111 1111 for the LTC1855 and between 0000 0000 0000 and 1111 1111 1111 for the LTC1854. For full-scale adjustment, an input voltage of FS - 1.5LSBs should be applied to the "+" input and the appropriate reference adjusted until the output code flickers between 0111 1111 1111 1110 and 0111 1111 1111 1111 for the LTC1856, between 01 1111 1111 1110 and 01 1111 1111 1111 for the LTC1855 and between 0111 1111 1110 and 0111 1111 1111 for the LTC1854. These adjustments as well as the factory trims affect all channels. The channel-to-channel offset and gain error matching are guaranteed by design to meet the specifications in the Converter Characteristics table. 185456fa 15 LTC1854/LTC1855/LTC1856 APPLICATIO S I FOR ATIO DC PERFORMANCE One way of measuring the transition noise associated with a high resolution ADC is to use a technique where a DC signal is applied to the input of the MUX and the resulting output codes are collected over a large number of conversions. For example in Figure 5 the distribution of output code is shown for a DC input that has been digitized 4096 times. The distribution is Gaussian and the RMS code transition is about 1LSB for the LTC1856. DIGITAL INTERFACE Internal Clock The ADC has an internal clock that is trimmed to achieve a typical conversion time of 4ms. No external adjustments are required and, with the maximum acquisition time of 4ms, throughput performance of 100ksps is assured. 3V Input/Output Compatible The LTC1854/LTC1855/LTC1856 operate on a 5V supply, which makes the devices easy to interface to 5V digital systems. These devices can also interface to 3V digital systems: the digital input pins (SCK, SDI, CONVST and RD) of the LTC1854/LTC1855/LTC1856 recognize 3V or 5V inputs. The LTC1854/LTC1855/LTC1856 have a dedi1800 1600 1400 1200 COUNT 1000 800 600 400 200 0 -4 -3 -2 -1 1 0 CODE 2 3 4 Figure 5. LTC1856 Histogram for 4096 Conversions 16 U cated output supply pin (OVDD) that controls the output swings of the digital output pins (SDO, BUSY) and allows the part to interface to either 3V or 5V digital systems. The SDO output is two's complement. Timing and Control Conversion start and data read are controlled by two digital inputs: CONVST and RD. To start a conversion and put the sample-and-hold into the hold mode bring CONVST high for at least 40ns. Once initiated it cannot be restarted until the conversion is complete. Converter status is indicated by the BUSY output, which goes low while the conversion is in progress. Figures 6a and 6b show two different modes of operation for the LTC1856. For the 12-bit LTC1854 and 14-bit LTC1855, the last four and two bits of the SDO will output zeros, respectively. In mode 1 (Figure 6a), RD is tied low. The rising edge of CONVST starts the conversion. The data outputs are always enabled. The MSB of the data output is available after the conversion. In mode 2 (Figure 6b), CONVST and RD are tied together. The rising edge of the CONVST signal starts the conversion. Data outputs are in three-state at this time. When the conversion is complete (BUSY goes high), CONVST and RD go low to enable the data output for the previous conversion. 185456 F05 W UU 185456fa RD = 0 t3 4 5 6 7 8 15 16 1 2 3 4 5 6 7 8 15 16 t5 t4 1 2 3 SCK tACQ X X NAP SLEEP DON'T CARE X X NAP SLEEP DON'T CARE t7 SHIFT A/D RESULT OUT AND NEW CONFIGURATION WORD IN B8 B1 B0 B11 B10 B9 B8 B1 B0 t1 t12 B15 (MSB) B14 B13 B12 t6 SGL/ DIFF ODD/ SIGN SELECT 1 SELECT 0 t10 t11 SDI DON'T CARE SGL/ DIFF ODD/ SIGN SELECT 1 SELECT 0 SHIFT CONFIGURATION WORD IN B12 B11 B10 B9 SDO B15 (MSB) B14 B13 t12 t2 BUSY tCONV 18545 F06a t9 t3 t13 CONVST = RD APPLICATIO S I FOR ATIO SCK tACQ X X NAP SLEEP DON'T CARE t7 Hi-Z B11 B10 B9 B8 t2 B1 B0 B15 (MSB) B14 t6 SHIFT A/D RESULT OUT AND NEW CONFIGURATION WORD IN B13 B12 B11 B10 B9 B8 B1 B0 Hi-Z SGL/ DIFF ODD/ SIGN SELECT 1 SELECT 0 X X NAP SLEEP DON'T CARE t10 t11 SDI DON'T CARE SGL/ DIFF ODD/ SIGN SELECT 1 SELECT 0 SHIFT CONFIGURATION WORD IN B12 SDO Hi-Z B15 (MSB) B14 B13 t8 BUSY tCONV 185456 F06b Figure 6b. Mode 2 for the LTC1856*. CONVST and RD Tied Together. CONVST Starts a Conversion, Data is Read by RD t13 t9 t3 RD t5 4 5 6 7 8 15 16 1 2 3 4 5 6 7 8 15 16 t4 1 2 3 SCK tACQ X X NAP SLEEP DON'T CARE t7 t6 SHIFT A/D RESULT OUT AND NEW CONFIGURATION WORD IN Hi-Z B11 B10 B9 B8 B1 B0 t1 B15 (MSB) B14 B13 B12 B11 B10 B9 B8 B1 B0 Hi-Z SGL/ DIFF ODD/ SIGN SELECT 1 SELECT 0 X X NAP SLEEP DON'T CARE t10 t11 SDI DON'T CARE SGL/ DIFF ODD/ SIGN SELECT 1 SELECT 0 SHIFT CONFIGURATION WORD IN SDO Hi-Z B15 (MSB) B14 B13 B12 t8 CONVST t2 BUSY tCONV 185456 F07 LTC1854/LTC1855/LTC1856 17 185456fa Figure 7. Operating Sequence for the LTC1856* *For the 12-bit LTC1854 and the LTC1855 the last four and two bits of the SDO will output zeros, respectively. U 6 7 8 15 16 t4 1 4 5 6 7 8 15 16 2 3 4 5 1 t5 2 3 W Figure 6a. Mode 1 for the LTC1856*. CONVST Starts a Conversion, Data Output is Always Enabled (RD = 0) UU CONVST LTC1854/LTC1855/LTC1856 APPLICATIO S I FOR ATIO SERIAL DATA INPUT (SDI) INTERFACE The LTC1854/LTC1855/LTC1856 communicate with microprocessors and other external circuitry via a synchronous, full duplex, 3-wire serial interface (see Figure 7). The shift clock (SCK) synchronizes the data transfer with each bit being transmitted on the falling SCK edge and captured on the rising SCK edge in both transmitting and receiving systems. The data is transmitted and received simultaneously (full duplex). An 8-bit input word is shifted into the SDI input which configures the LTC1854/LTC1855/LTC1856 for the next conversion. Simultaneously, the result of the previous conversion is output on the SDO line. At the end of the data exchange the requested conversion begins by applying a rising edge on CONVST. After tCONV, the conversion is complete and the results will be available on the next data transfer cycle. As shown below, the result of a conversion Table 1. Multiplexer Channel Selection MUX ADDRESS SGL/ ODD SELECT DIFF SIGN 1 0 0 0 00 0 0 01 0 0 10 0 0 11 0 1 00 0 1 01 0 1 10 0 1 11 DIFFERENTIAL CHANNEL SELECTION 0 + 1 - + - + - + - + - + - + - + - 2 3 4 5 6 7 MUX ADDRESS SGL/ ODD SELECT DIFF SIGN 1 0 1 0 00 1 0 01 1 0 10 1 0 11 1 1 00 1 1 01 1 1 10 1 1 11 SINGLE-ENDED CHANNEL SELECTION 0 + + + + + + + + 1 2 3 4 5 6 7 COM - - - - - - - - 4 Differential CHANNEL 0,1 8 Single-Ended CHANNEL 0 1 2 3 4 5 6 7 { { { { 2,3 + (-) - (+) + (-) - (+) + (-) - (+) + (-) - (+) 4,5 + + + + + + + + COM (-) 6,7 Figure 8. Examples of Multiplexer Options on the LTC1854/LTC1855/LTC1856 185456fa 18 U is delayed by one conversion from the input word requesting it. SDI SDO SDI WORD 1 SDO WORD 0 DATA TRANSFER tCONV A/D CONVERSION SDI WORD 2 SDO WORD 1 DATA TRANSFER tCONV A/D CONVERSION SDI WORD 3 SDO WORD 2 18545 AI02 W UU INPUT DATA WORD The LTC1854/LTC1855/LTC1856 8-bit data word is clocked into the SDI input on the first eight rising SCK edges. Further inputs on the SDI pin are then ignored until the next conversion. The eight bits of the input word are defined as follows: SGL/ DIFF ODD SIGN SELECT 1 SELECT 0 DON'T CARE DON'T CARE NAP SLEEP MUX ADDRESS POWER DOWN SELECTION 18545 AI03 Combinations of Differential and Single-Ended CHANNEL 0,1 Changing the MUX Assignment "On the Fly" { { 4 5 6 7 + - - + + + + + COM (-) 4,5 2,3 { { 6,7 + - + - COM (UNUSED) 1ST CONVERSION 4,5 { 6 7 - + + + COM (-) 2ND CONVERSION 18545 F08 LTC1854/LTC1855/LTC1856 APPLICATIO S I FOR ATIO MUX ADDRESS The first four bits of the input word assign the MUX configuration for the requested conversion. For a given channel selection, the converter will measure the voltage between the two channels indicated by the + and - signs in the selected row of Table 1. Note that in differential mode (SGL/DIFF = 0) measurements are limited to four adjacent input pairs with either polarity. In single-ended mode, all input channels are measured with respect to COM. Both the "+" and "-" inputs are sampled simultaneously so common mode noise is rejected. Bits 5 and 6 of the input words are Don't Care bits. POWER DOWN SELECTION (NAP, SLEEP) The last two bits of the input word (Nap and Sleep) determine the power shutdown mode of the LTC1854/LTC1855/ LTC1856. See Table 2. Nap mode is selected when Nap = 1 and Sleep = 0. The previous conversion result will be clocked out and a conversion will occur before entering the Nap mode. The Nap mode starts at the end of the conversion which is indicated by the rising edge of the BUSY signal. Nap mode lasts until the falling edge of the 2nd SCK (see Figure 9). Automatic nap will be achieved if Nap = 1 is selected each time an input word is written to the ADC. Table 2. Power Down Selection NAP 0 1 X SLEEP 0 0 1 POWER DOWN MODE Power On Nap Sleep U Sleep mode will occur when Sleep = 1 is selected, regardless of the selection of the Nap input. The previous conversion result can be clocked out and the Sleep mode will start on the falling edge of the last (16th) SCK. Notice that the CONVST should stay either high or low in sleep mode (see Figure 10). To wake up from the sleep mode, apply a rising edge on the CONVST signal and then apply Sleep = 0 on the next SDI word and the part will wake up on the falling edge of the last (16th) SCK (see Figure 11). In Sleep mode, all bias currents are shut down and only the power on reset circuit and leakage currents (about 10mA) remain. Sleep mode wake-up time is dependent on the value of the capacitor connected to the REFCOMP (Pin 16). The wake-up time is typically 40ms with the recommended 10mF capacitor connected on the REFCOMP pin. DYNAMIC PERFORMANCE FFT (Fast Fourier Transform) test techniques are used to test the ADC's frequency response, distortion and noise at the rated throughput. By applying a low distortion sine wave and analyzing the digital output using an FFT algorithm, the ADC's spectral content can be examined for frequencies outside the fundamental. Figure 12 shows a typical LTC1856 FFT plot which yields a SINAD of 87dB and THD of - 101dB. 185456fa W UU 19 RD BUSY tACQ tCONV NAP tACQ 18545 F09 RD APPLICATIO S I FOR ATIO 1 3 4 5 6 7 8 15 16 2 U 18545 F10 LTC1854/LTC1855/LTC1856 SCK SDI SHIFT SLEEP CONFIGURATION WORD IN B13 B12 B11 B10 B9 B8 B0 B1 A/D RESULT FROM PREVIOUS CONVERSION CONVST SHOULD STAY EITHER HIGH OR LOW IN SLEEP MODE DON'T CARE SELECT 1 SELECT 0 X X NAP DON'T CARE SLEEP = 1 SGL/ DIFF ODD/ SIGN SDO B15 (MSB) B14 CONVST tCONV SLEEP BUSY Figure 10. Sleep Mode Operation for the LTC1856* RD 1 3 4 5 6 7 8 15 16 2 1 2 3 4 5 6 7 8 15 16 SCK SDI SHIFT WAKE-UP CONFIGURATION WORD IN B13 B12 B11 B10 B9 B8 A/D RESULT NOT VALID B1 DON'T CARE SELECT 1 SELECT 0 X X NAP DON'T CARE SGL/ DIFF ODD/ SIGN SLEEP = 0 SGL/ DIFF ODD/ SIGN SELECT 1 SELECT 0 X X NAP SLEEP SHIFT A/D RESULT OUT AND NEW CONFIGURATION WORD IN B0 B15 (MSB) B14 B13 B12 B11 B10 B9 B8 DON'T CARE SDO B15 (MSB) B14 B1 B0 CONVST tCONV 18545 F11 tCONV BUSY SLEEP WAKE-UP TIME READY 185456fa Figure 11. Wake Up from Sleep Mode for the LTC1856* *For the 12-bit LTC1854 and 14-bit LTC1855 the last four and two bits of the SDO will output zeros, respectively. W Figure 9. Nap Mode Operation for the LTC1856* UU 20 5 6 7 8 15 16 1 2 3 4 5 6 7 8 15 16 X X NAP = 1 SLEEP = 0 DON'T CARE X X NAP SLEEP DON'T CARE SHIFT A/D RESULT OUT FROM PREVIOUS CONVERSION AND NEW CONFIGURATION WORD IN Hi-Z B11 B10 B9 B8 B11 B10 B9 B8 B1 B0 B1 B0 B15 MSB B14 B13 B12 Hi-Z SGL/ DIFF ODD/ SIGN SELECT 1 SELECT 0 1 2 3 4 SCK SDI DON'T CARE SGL/ DIFF ODD/ SIGN SELECT 1 SELECT 0 SHIFT CONFIGURATION WORD IN SDO Hi-Z B15 (MSB) B14 B13 B12 CONVST LTC1854/LTC1855/LTC1856 APPLICATIO S I FOR ATIO SIGNAL-TO-NOISE AND DISTORTION RATIO The Signal-to-Noise and Distortion Ratio (SINAD) is the ratio between the RMS amplitude of the fundamental input frequency to the RMS amplitude of all other frequency components at the A/D output. The output is band limited to frequencies from above DC and below half the sampling frequency. Figure 12 shows a typical SINAD of 87dB with a 100kHz sampling rate and a 1kHz input. TOTAL HARMONIC DISTORTION Total Harmonic Distortion (THD) is the ratio of the RMS sum of all harmonics of the input signal to the fundamental itself. The out-of-band harmonics alias into the frequency band between DC and half the sampling frequency. THD is expressed as: V22 + V32 + V42 ... + VN2 THD = 20log V1 where V1 is the RMS amplitude of the fundamental frequency and V2 through VN are the amplitudes of the second through Nth harmonics. 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 0 5 MAGNITUDE (dB) Figure 12. LTC1856 Nonaveraged 4096 Point FFT Plot U BOARD LAYOUT, POWER SUPPLIES AND DECOUPLING Wire wrap boards are not recommended for high resolution or high speed A/D converters. To obtain the best performance from the LTC1854/LTC1855/LTC1856, a printed circuit board is required. Layout for the printed circuit board should ensure the digital and analog signal lines are separated as much as possible. In particular, care should be taken not to run any digital track alongside an analog signal track or underneath the ADC. The analog input should be screened by AGND. In applications where the MUX is connected to the ADC, it is possible to get noise coupling into the ADC from the trace connecting the MUXOUT to the ADC. Therefore, reducing the length of the traces connecting the MUXOUT pins (Pins 10, 11) to the ADC pins (Pins 12, 13) can minimize the problem. The unused MUX inputs should be grounded to prevent noise coupling into the inputs. Figure 13 shows the power supply grounding that will help obtain the best performance from the 12-bit/14-bit/16-bit ADCs. Pay particular attention to the design of the analog and digital ground planes. The DGND pin of the LTC1854/ fSAMPLE = 100kHz fIN = 1kHz SINAD = 87dB THD = -101dB 10 15 20 25 30 35 40 45 50 FREQUENCY (kHz) 185456 F12 W UU 185456fa 21 LTC1854/LTC1855/LTC1856 APPLICATIO S I FOR ATIO LTC1855/LTC1856 can be tied to the analog ground plane. Placing the bypass capacitor as close as possible to the power supply pins, the reference and reference buffer output is very important. Low impedance common returns for these bypass capacitors are essential to low noise operation of the ADC, and the foil width for these tracks should be as wide as possible. Also, since any potential difference + - LTC1854/ LTC1855/ CH0 LTC1856 10 12 CH1 MUXOUT + ADC+ CH2 LTC1854/LTC1855/LTC1856 CH3 CH4 ADC- MUXOUT - VREF REFCOMP AGND AVDD DVDD DGND 11 13 CH5 CH6 15 16 14, 17, 18 19 20 24 CH7 10F 10F 10F 1F COM ANALOG GROUND PLANE Figure 13. Power Supply Grounding Practice 22 U in grounds between the signal source and ADC appears as an error voltage in series with the input signal, attention should be paid to reducing the ground circuit impedance as much as possible. The digital output latches and the onboard sampling clock have been placed on the digital ground plane. The two ground planes are tied together at the ADC through a wide, low inductance path. DIGITAL SYSTEM OVDD 21 10F DIGITAL GROUND PLANE 18545 F13 W UU 185456fa LTC1854/LTC1855/LTC1856 PACKAGE DESCRIPTIO U G Package 28-Lead Plastic SSOP (5.3mm) (Reference LTC DWG # 05-08-1640) 9.90 - 10.50* (.390 - .413) 28 27 26 25 24 23 22 21 20 19 18 17 16 15 1.25 0.12 5.3 - 5.7 7.40 - 8.20 (.291 - .323) 0.65 BSC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 2.0 (.079) MAX 0 - 8 7.8 - 8.2 0.42 0.03 RECOMMENDED SOLDER PAD LAYOUT 5.00 - 5.60** (.197 - .221) 0.09 - 0.25 (.0035 - .010) 0.55 - 0.95 (.022 - .037) 0.65 (.0256) BSC NOTE: 1. CONTROLLING DIMENSION: MILLIMETERS MILLIMETERS 2. DIMENSIONS ARE IN (INCHES) 3. DRAWING NOT TO SCALE *DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED .152mm (.006") PER SIDE **DIMENSIONS DO NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED .254mm (.010") PER SIDE 0.22 - 0.38 (.009 - .015) TYP 0.05 (.002) MIN G28 SSOP 0204 185456fa Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. 23 LTC1854/LTC1855/LTC1856 TYPICAL APPLICATIO 5V 10F 19 AVDD 1 COM 2 CH0 SINGLE-ENDED OR DIFFERENTIAL CHANNEL SELECTION (SEE TABLE 1) INPUT RANGE: 10V 3 CH1 INTERNAL CLOCK MUX ADDRESS CONTROL LOGIC 0.1F 20 DVDD CONVST 28 SDI 25 BUSY 22 8-BIT SERIAL DATA INPUT 10F 0.1F * * * 9 CH7 INPUT MUX AGND1 MUXOUT- 14 11 RELATED PARTS PART NUMBER Sampling ADCs LTC1418 LTC1604 LTC1605 LTC1606 LTC1608 LTC1609 LTC1850/LTC1851 LTC1859/LTC1858/ LTC1857 LTC1864/LTC1865 LTC1864L/LTC1865L DACs LTC1588/LTC1589 LTC1592 LTC1595 LTC1596 LTC1597 LTC1650 LTC2704-16/ LTC2704-14/ LTC2704-12 DESCRIPTION 14-Bit, 200ksps, Single 5V or 5V ADC 16-Bit, 333ksps, 5V ADC 16-Bit, 100ksps, Single 5V ADC 16-Bit, 250ksps, Single 5V ADC 16-Bit, 500ksps, 5V ADC 16-Bit, 200ksps Serial ADC 10-Bit/12-Bit, 8-Channel, 1.25Msps ADC 16-Bit, 14-Bit, 12-Bit, 100ksps, SoftSpan ADCs 16-Bit, 1-/2-Channel, 250ksps ADC in MSOP 3V, 16-Bit, 1-/2-Channel, 150ksps ADC in MSOP COMMENTS 15mW, Serial/Parallel I/O 90dB SINAD, 220mW Power Dissipation, Pin Compatible with LTC1608 10V Inputs, 55mW, Byte or Parallel I/O, Pin Compatible with LTC1606 10V Inputs, 75mW, Byte or Parallel I/O, Pin Compatible with LTC1605 90dB SINAD, 270mW Power Dissipation, Pin Compatible with LTC1604 Configurable Unipolar/Bipolar Input, Up to 10V Single 5V Supply Programmable MUX and Sequencer, Parallel I/O Software-Selectable Spans, Pin Compatible with Single 5V Supply, 850mA with Autoshutdown Single 3V Supply, 450mA with Autoshutdown LTC1856/LTC1855/LTC1854 Software-Selectable Spans, 1LSB INL/DNL 1LSB Max INL/DNL, Low Glitch, DAC8043 16-Bit Upgrade 1LSB Max INL/DNL, Low Glitch, AD7543/DAC8143 16-Bit Upgrade 1LSB Max INL/DNL, Low Glitch, 4 Quadrant Resistors Low Power, Low Glitch, 4-Quadrant Multiplication Software-Selectable Spans, 2LSB INL, 1LSB INL, Force/Sense Output 12-/14-/16-Bit, Serial, SoftSpan IOUT DACs 16-Bit Serial Multiplying IOUT DAC in SO-8 16-Bit Serial Multiplying IOUT DAC 16-Bit Parallel, Multiplying DAC 16-Bit Serial VOUT 5V DAC 16-Bit, 14-Bit, 12-Bit, Serial, Quad SoftSpan VOUT DACs 24 Linear Technology Corporation 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408) 432-1900 FAX: (408) 434-0507 U 5V SCK 26 16 SHIFT CLOCK CYCLES + 12-/14-/16-BIT SAMPLING ADC DATA OUT SERIAL I/O 4.096V 2.5V REFERENCE 1.6384X RD 27 OVDD 21 10F SDO 23 16-BIT SERIAL DATA OUT 0.1F 3V TO 5V - 8k MUXOUT+ 10 ADC+ 12 ADC- 13 VREF 15 1F 10F REFCOMP 16 0.1F AGND2 AGND3 DGND 17 18 24 18545 TA03 185456fa LT 0407 REV A * PRINTED IN THE USA www.linear.com LINEAR TECHNOLOGY CORPORATION 2006 |
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